Arithmetic Operator Verilog Code

module arithmetic_operators(a,b,add,sub,div,mul,mod);

input [3:0]a,b;

output [7:0]add,sub,div,mul,mod;

assign add=a+b;

assign sub=a-b;

assign div=a/b;

assign mul=a*b;

assign mod=a%b;

endmodule

module test_arithmetic_operators;

reg [3:0]a,b;

wire [7:0]add,sub,div,mul,mod;

arithmetic_operators b1(a,b,add,sub,div,mul,mod);

initial

begin

a = 4'b0111; b = 4'b0101;

#20 a = 4'b0111; b = 4'b0101;

end

endmodule

Technical Khawar