Bitwise Operator Example using Verilog Code

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 Bitwise Operator using Verilog Example Code

module bitwise_and(a,b,c);

input [1:0]a,b;

output [1:2]c;

assign c=a&b;

endmodule

module test_bitwiseand;

reg [1:0]a,b;

wire [1:2]c;

bitwise_and b1(a,b,c);

initial

begin

     a=2'b00; b=2'b00;

# 20 a=2'b00; b=2'b01;

# 20 a=2'b00; b=2'b10;

# 20 a=2'b11; b=2'b11;

# 20 a=2'b11; b=2'b11;

end

endmodule

 Output (Wave & Dataflow diagram)

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