Concatenation & Replication Operator Example Code using Verilog

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Concatenation & Replication Operator using Verilog Example Code

module Concatenation_Operator(a,b,c);

input [1:0]a;

input [1:0]b;

output [7:0]c;

assign c={2{a,b}};

endmodule

 

module test_Concatenation_Operator;

 

reg [1:0]a;

reg [1:0]b;

wire [7:0]c;

Concatenation_Operator b1(a,b,c);

initial

begin

     a=2'b10; b=2'b01;

#20  a=2'b10; b=2'b01;

 

end

endmodule

 Output (Wave & Dataflow diagram)

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