Logical Operator Example Code using Verilog

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Logical Operator using Verilog Example Code

module Logical_OR(a,b,c);

input a,b;

output c;

assign c = a||b;

endmodule

 

module test_Logical_OR;

reg a,b;

wire c;

Logical_OR b1(a,b,c);

initial

begin

     a=1'b0; b=1'b0;

# 20 a=1'b0; b=1'b1;

# 20 a=1'b1; b=1'b0;

# 20 a=1'b1; b=1'b1;

# 20 a=1'b1; b=1'b1;

end

endmodule

 Output (Wave & Dataflow diagram)

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