Reduction Operator Example Code using Verilog

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Reduction Operator using Verilog Example Code

module Reduction_XNOR(a,c);

input [1:0]a;

output c;

assign c = ^~a;

endmodule

 

module test_Reduction_XNOR;

 

reg [1:0]a;

wire c;

Reduction_XNOR b1(a,c);

initial

begin

     a=2'b00;

# 20 a=2'b01;

# 20 a=2'b10;

# 20 a=2'b11;

# 20 a=2'b11;

end

endmodule

 Output (Wave & Dataflow diagram)

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