Relational Operator Code using Verilog

Relational Operator Program using Verilog Code

module Relational_Greater(a,b,c); input [3:0]a,b; output [5:2]c; assign c=a>b; endmodule module test_Relational_Greater; reg [3:0]a,b; wire [5:2]c; Relational_Greater b1(a,b,c); initial begin      a = 4'd3; b = 4'd2; #20  a = 4'd2; b = 4'd6; #20  a = 4'd2; b = 4'd6; end endmodule  Output (Wave & Dataflow diagram)