Shift Operator Example Code using Verilog

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Shift Operator using Verilog Example Code

module Shift_Left(a,c);

input [3:0]a;

output [7:4]c;

assign c = a<<1;

endmodule

 

module test_Shift_Left;

 

reg [3:0]a;

wire [7:4]c;

Shift_Left b1(a,c);

initial

begin

     a=4'b0000;

# 20 a=4'b1111;

# 20 a=4'b1111;

end

endmodule

 Output (Wave & Dataflow diagram)


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